SystemVerilog Design and Verification Tools

The tool set helps the user fulfill the design and verification tasks with great productivity. The intelligent navigators alleviate the user's typing burden. The versatile SystemVerilog compiler compiles SystemVerilog description background as the user makes code. Typographical and syntactical errors are fixed during the code entry.

The process from compilation to simulation of the design is fully automated. The design manager collects necessary files and resources to run the process. The simulator is a compiled SystemVerilog simulator.

Verification functions are all supported, including assertions, functional coverage, constrained random value generation. Code coverage is also supported. The verification viewers visualize the verification results effectively. The tool set is a low-cost IDE solution to the SystemVerilog users.

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